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This blog provides an overview of Makerchip Flows, which is a suite of EDA Flows created for taking TL-Verilog/Verilog designs through various ASIC/FPGA Design pathways and also provides a high-level picture of the frameworks developed.
To minimize the redundancy of information, links have been provided to my Github repos which have step-by-step instructions for readers interested in trying out Makerchip Flows
Introduction
The success of a new design language and its eco-system not only lies in its inherent novelty but also in the ability to interoperate with existing, and established commercial and Open source EDA Tools. RedwoodEDA’s Makerchip is a powerful web-based IDE that provides a unique chip design and verification platform. While supporting the novel TL-Verilog language, and also supporting Verilog/SystemVerilog, Makerchip has become an attractive option for designers, students, and even beginners looking to build hardware systems quickly and easily. While, many commercial EDA (Electronic Design Automation) tools, offer advanced features for a proficient user, open-source EDA tools are increasingly popular for their flexibility and cost-effectiveness among students and beginners. “Makerchip Flows” would be a suite of integrations to both Open-source and Commercial EDA tools, providing a rapid ASIC/FPGA prototyping flow or integration to any third-party EDA tools.
To address these needs, Makerchip Flows adds support for commercial and open-source EDA tools, allowing designers, beginners, or any user of Makerchip to design, simulate, and visualize on the browser, and take one's design to the ASIC, FPGA, Verification, or third-party flows platform agnostically without worrying about tool-specific scripts. This will include scripts that support synthesis, FPGA development, and Simulation with commercial and open-source tool flows. Some of the popular commercial EDA tools that will be supported include Cadence, Synopsys, and Mentor Graphics. Open-source EDA tools and tool flows like F4PGA, OpenLane, etc., will also be supported. Overall, Makerchip flows mainly treat TL-Verilog to Verilog as a "front-end" for any flows, enabling the creation of new flows according to the user's needs.
There are several reasons why this versatile interoperability is essential for chip designers. Firstly, it allows designers to use their preferred tools within a single environment, streamlining the design process and reducing the risk of errors caused by tool incompatibility, having to spend extensive manpower on vendor-specific EDA tooling and commands. This will save designers a significant amount of time and effort in the long run, as they won't have to switch between different environments or learn new tools to achieve their goals. Makerchip, which also has the ability to edit files locally enables a hybrid web-local approach leading towards a higher degree of interoperability with other EDA tools.
Overall, the addition of support for commercial and open-source EDA tools in Makerchip is a significant step towards making chip design more accessible, with reduced complexity of entry. By providing a versatile and interoperable platform, Makerchip is making it easier for designers to build complex hardware systems with their preferred tools, while also lowering the barrier to entry for new designers. With this new functionality, Makerchip along with Makerchip Flows will be well-positioned to become a go-to platform for chip design.
Makerchip Flows
"Makechip-Flows" is an umbrella term, that encompasses EDA flows that use Makerchip as the front-end interface for Design/Verification/Simulation/Visualization and invoke the Makerchip-backend to perform transformations on the design (netlist/bitstream/GDSII etc.,). The capabilities of the Makerchip flows are supported by interfacing with tools on the cloud (Sandpiper-SaaS™, which is a TL-Verilog compiler (Sandpiper™) as a microservice) and tools installed locally (any supported open-source/commercial EDA tools).
The backbone of Makerchip Flows
Edalize - It is a Python-based abstraction library that provides a common EDAM (EDA Metadata) API between EDA tools. Edalize backend support can be added for, any EDA tool and EDA Flows can be created. EDA Flow refers to multiple EDA tools working together to produce an end product, which can be a netlist, bitstream, High-Level HDL to Verilog/VHDL, GDSII, PPA reports, Linters, Formal reports, or any output from the final EDA tool in the flow.
Fusesoc - It is a build system for digital hardware and a package manager for hardware projects. Fusesoc uses Edalize in the backend. When the support for a tool, or when a new flow is created in Edalize it can be used in Fusesoc.
Reason for choosing Edalize and Fusesoc
While semiconductor companies have their internal flows to interface with EDA tools, create flows, and automate tasks, Edalize and Fusesoc are among the most popular EDA tools, in the open-source community, which have been around for over a decade and even has been adopted by several companies to construct their internal tools. In addition to its popularity the modular architecture of Edalize-Fusesoc is one of the main reasons to make this choice over other frameworks like SiliconCompiler.
Support for Sandpiper-SaaS™ in SiliconCompiler
Support for Sandpiper-SaaS™ has also been added to SiliconCompiler which can be used by installing Siliconcompiler from this repo. An example of using Sandpiper™ as a front-end for SiliconCompiler-based flows has been provided here. This example takes the TLV-based design to GDSII on Skywater 130nm PDK (or) FreePDK 45.
Similar to the example provided the user can create/use any flows supported in SiliconCompiler to generate a bitstream for FPGAs, use other PDKs, etc., This support can be leveraged in the future for basing Makerchip flows based on Silicon Compiler.
Using Makerchip Flows
Edalize-FuseSoC is chosen as the main framework to form the foundation of Makerchip Flows. Following are the capabilities added to Edalize, to support new tools, front-ends and flows in Edalize.
Please install Edalize from my fork, while the outstanding pull requests are merged to the main repository. If you already have an Edalize version installed on your machine, it is recommended that you create a Python virtual environment and install Edalize from the below link FIRST and then install Fusesoc from the official repository
Edalize: https://github.com/shariethernet/my_edalize
This version of Edalize has
Support for Sandpiper™ in the Flow API (TLV as a front-end)
Synopsys Design Compiler
Synopsys Primetime
Synopsys Primepower
Example Flows with Sandpiper™->DesignCompiler, Sandpiper™->DesignCompiler->PrimeTime etc.,
Once you have installed the above packages, please refer to the GitHub links, and then refer to the associated READMEs linked in the text to try out the flows or create your own.
Github: https://github.com/TL-X-org/tlvflows
Makerchip Flows, more generally known as TLV Flows can be classified into two categories based on the front end used. The fundamental difference between the two flows is that Makerchip Flows always has a makerchip-specific top module that enables the designer to use all the features of Makerchip IDE like Visualizations, automatic test vector generation, cloud-based simulation in Verilator, view waveforms, etc.,
For production (ASIC GDSII or FPGA Bitstream), this top module should be modified according to the user's needs.
When you develop locally with your IDE and use Sandpiper-SaaS™/ Sandpiper™ for compiling TL-V Code, Generic Flows are used. Any flow in the makerchip flows can be used in the generic flows without any modification.
Following are some of examples flows that can be used
TLV to SV: This can be used to convert TL-Verilog to SystemVerilog/ Verilog (either using the tool/Flow API).
Synthesis Flow: This takes a user's TL-Verilog design, SDC file, and library files and gives the synthesized netlist. It uses Sandpiper™ for TL-V to SV/V conversion and Synopsys Design Compiler for Synthesis.
Power Analysis Flow: This takes a user's TL-Verilog design, SDC file, library files, and waveforms (VCD/FSDB/SAIF) to perform vector-based power simulation either by propagating the activity of the RTL simulations on the gate-level netlist, or using the gate level simulation waveforms on the gate-level netlist.
FPGA Flow: This takes a user's TL-Verilog design, and SDC file and generates the bitstream for a selected Xilinx FPGA part. It uses the Sandpiper™ to process TL-V and Vivado to generate the bitstream.
The Synthesis, Power Analysis Flow, and FPGA Flows can be used as a reference flow to create new flows using other supported tools in Edalize or by referring to the support for Design Compiler/ PrimeTime-PrimePower to add support for tools and creating flows.
Makerchip Flows uses Makerchip top module for the design and Makerchip's test benches to perform simulation (leveraging Makerchip's automatic test vector generation). One can also use these flows to perform simulations with their own test benches. Currently, VCS, Verilator, Icarus, Questasim, and Xcelium are supported (as they are pre-included in the Edalize package)
VIZPA
VIZPA is a visualization framework that can be used to visualize the area of a synthesized RTL as a treemap, and the results of vector-based/averaged power analysis as a heatmap on the treemap. Currently, this tool supports Synopsys Design Compiler and Synopsys PrimePower. But can be extended by adding support only for the parser function to other open-source or commercial EDA tools.
GitHub Link: https://github.com/shariethernet/vizpa
Acknowledgments
Sincere thanks to Steve Hoover - Founder, Redwood EDA for the extensive mentorship, guidance, and support throughout this project
Credits to CHIPS Alliance for sponsoring this project via Google Summer of Code 2023.
(DISCLAIMER: Any trademarks, and logos used here are properties of their respective owners, and their inclusion in this blog post does not imply endorsement or affiliation by the owner of the artifact unless explicitly stated.)
